Conventionally, as one of the techniques coping with the miniaturization and higher integration of semiconductor elements mounted on a semiconductor device, the SOI (Silicon On Insulator) technique has been known. This technique is a technique for forming a single-crystal silicon film on an insulative substrate, where isolation among semiconductor elements is realizable almost completely. Thus, this technique has advantages that (i) it is easy to cope with the miniaturization and higher integration of semiconductor elements and that (ii) it is easily possible to cope with speedup of operation because parasitic capacitance between the elements and the substrate is lowered.
Moreover, with the recent semiconductor devices, speedup of the operation are progressing along with miniaturization and higher integration of the semiconductor elements and thus, the operating frequency of the elements has entered the order of GHz. Further, because the size itself of the chip of a semiconductor device (i.e., a semiconductor chip) increases with the rising integration level, there is a growing tendency that wiring lines interconnecting semiconductor elements located on the semiconductor chip (i.e., on-chip wiring lines), and the characteristics of the substrate (e.g., wiring resistance and parasitic capacitance of the wiring lines and the substrate) determine the performance of the semiconductor device.
With the recent semiconductor devices, to cope with such the tendency as above, wiring lines are shifting from aluminum (Al) lines to copper (Cu) lines in order to lower their electric resistance. Moreover, to reduce the parasitic resistance to suppress the signal transmission delay, an insulator material film having a lower dielectric constant (e.g., the relative dielectric constant is equal to 3 or lower) is adopted as the interlayer insulator film and at the same time, the wiring structure is shifting from a single-layer wiring to a multilayer wiring structure.
The above-described conventional techniques can cope with the speedup of operation to a certain extent. However, if the operating frequency enters the order of GHz, these conventional techniques are unable to realize it easily. This is because signal transmission delay induced by the parasitic resistance and parasitic capacitance of the single-crystal silicon substrate itself is elicited.
Response to the operating frequency in the order of GHz is realizable if a semiconductor substrate (e.g., a GaAs substrate) other than a single-crystal silicon substrate is used. If so, however, there arises another problem that the fabrication cost is higher, the integration scale is unable to be raised, and so on.